This application claims priority to Korean Patent Application No. 2006-09903, filed on Feb. 2, 2006 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to pulse width modulation, and more particularly to pulse width modulation with improved signal-to-noise ratio and total harmonic distortion in a digital power amplifier.
2. Background of the Invention
A pulse width modulation (PWM) circuit of a digital power amplifier generally receives pulse-code-modulated digital audio data, that is, pulse code modulation (PCM) data. The PCM data may be directly modulated to a PWM signal in a digital domain, or may be modulated to the PWM signal after reducing a number of bits of the PCM data using sigma-delta modulation (SDM) and the like.
A PWM method includes controlling an amplitude of an output signal according to duty cycle of the PWM signal. The PWM method is synchronized according to an input period of PCM data or a switching period of a class D amplifier switched by the PWM signal. In addition, a pulse generated by the PWM method may be symmetric or asymmetric based on the center of the switching period.
FIGS. 1 and 2 are timing diagrams illustrating conventional PWM methods. FIG. 1 shows 4-bit PCM data having a value from “−8” to “7”. A count signal is generated from counting from “−8” (1000) to “+7” (0111), and a period of the count signal corresponds to a switching period of a PWM signal. The count signal is comprised of sixteen time intervals with each time interval being for each count from “−8” (1000) to “+7” (0111).
The center of the count signal is at the beginning of when the count signal corresponds to “0” (0000). An asymmetric PWM signal is at a logic high state for eight time intervals to the left of the center of the count signal, and is at a logic low state for eight time intervals to the right of the center of the count signal. A symmetric PWM signal is at the logic high state for four time intervals respectively to the left and right of the center of the count signal, and is at the logic low state for the other eight time intervals. The symmetric PWM signal typically has less switching noise in comparison with the asymmetric PWM signal.
FIG. 2 shows 3-bit PCM data having a value from “−4” (100) to “+3” (011) and a count signal similar to FIG. 1. In FIG. 2, a PWM signal is input twice and is switched twice in one period of the count signal. Thus, a switching frequency is doubled, and noise due to the switching frequency may be decreased in an audio frequency band.
A PWM method in FIG. 2 includes reducing a number of bits of the PCM data and raising the switching frequency. Thus, the PWM signal according to the PWM method of FIG. 2 may have a high signal-to-noise ratio (SNR) and a low total harmonic distortion (THD) in comparison with the PWM method of FIG. 1. However, quantization error of the PWM signal of FIG. 2 may be larger than the PWM signal of FIG. 1.
Korean Patent Laid-Open Publication No. 2005-112649 discloses a PWM method in which a period of PCM data is the same as a period of a count signal, and in which a switching period of a generated PWM signal is twice the period of the count signal. According to that PWM method, the number of bits of the PCM data is maintained and the switching period of the PWM signal is raised so that quantization error of the PWM signal may be maintained and the PWM signal may have a relatively high SNR and a low THD.
However, according to the method disclosed in Korean Patent Laid-Open Publication No. 2005-112649, two PWM pulses generated from one PCM data may have pulse widths that are different from each other, so that noise may result due to these asymmetric pulses.